TC3299A Datasheet, PDF (4/26 Pages) List of Unclassifed Manufacturers – Ethernet PCMCIA Controller + COMBO Transceiver

1 Pin Description
Pin No. Symbol
ISA Bus Interface Pins
2-11
SA0-SA9
27-34
93-86
SD0-SD7
SD8-SD15
35
RST
26
WAIT*
24
REG*
21
IOR*
22
IOW*
23
OE*
1
WE*
96
INPACK*
95
IO16*
97
INT*
20
CE1*
TC3299A
Preliminary Data Sheet
I/O
Description
I These address signal lines of PCMCIA Bus are used to select a
register to be read or written and attribute memory enable.
I/O Register Access, with DMA inactive, SD0-SD7 pins are used to
I/O read/write register data. SD8-SD15 pins are invalid during this state.
Remote DMA Bus Cycle, SD0-SD15 pins contain packet data.
Direction of transfer is depended on Remote read/write.
I Reset pin. RST is active high and placed EPCC in a reset mode
immediately. During falling edge, the EPCC controller loads the
configuration from MD0-7, MA0-13.
O This pin is set low to insert wait states during Remote DMA transfer.
I REG* is an active low input used to determine whether a lost access is
to Attribute memory (The first 1K) or to common memory (above 1K).
If REG* is set to low the access is to attribute memory, while REG* is
set to high the access is to common memory. REG* is also asserted
low for all accesses to the TC3299A's IO Registers.
I Read Strobe: Strobe from host to read internal registers or Remote
DMA read.
I Write Strobe: Strobe from host to write internal registers or Remote
DMA write.
I Host memory read strobe. The attribute memory can be read when
OE* and REG* are both at low state.
While for Common memory to be accessed, OE* should be set to low
state and REG* should set to high state.
OE*
REG*
Attribute Memory Low
Low
Common Memory Low
High
I Host memory write strobe. After Power reset, if TC3299A is configured
to memory write enable, then 2 types of memories are written as
defined below:
WE*
REG*
Attribute Memory Low
Low
Common Memory Low
High
O Active low signal, asserted if the host access TC3299A internal
register or Remote DMA read cycle.
O IO16* is driven by EPCC to support host 16 bits access cycle.
O Interrupt:Indicates that the EPCC requires host attention after
reception, transmission or completion of DMA transfer.
I Card enable 1, are active low signals driven by the host. These signals
provide a card select based on an address decode (decode by the
host).
Confidential.
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Copyright © 2003, IC Plus Corp.
August 27, 20003
TC3299A-DS-R30