TC3299A Datasheet, PDF (11/26 Pages) List of Unclassifed Manufacturers – Ethernet PCMCIA Controller + COMBO Transceiver

TC3299A
Preliminary Data Sheet
3 Configuration Registers
Configuration Register A (R/W)
To prevent any accidental write of this register, it is ”hidden” behind a previously unused register. Register
0AH in the EPCC Controller's Page 0 of registers was previously reserved on a read. Now Configuration
Register A can be read at that address and can be written to by following a read to 0AH with a write to 0AH.
If any other ENCC Controller register accesses take place between the read and the write then the write
to 0AH will access the Remote Byte Count Register 0.
7
6
5
4
3
2
1
0
XX FREAD XX
XX
XX
XX
XX
XX
FREAD :The ENCC Controller supports 4 words Remote DMA read/write cache. When this bit is set
high,Remote DMA cache control will be enabled.
XX :Reserved
Configuration Register B (R/W)
To prevent any accidental write of this register, it is ”hidden” behind a previously unused register.
Register 0BH in the EPCC Controller's Page 0 of registers was previously reserved on a read. Now
Configuration Register B can be read at that address and can be written to by following a read to 0BH
with a write to 0BH.
If any other ENCC Controller register accesses take place between the read and the write then the write
to 0BH will access the Remote Byte Count Register 1.
7
6
5
XX LINK XX
4
3
2
1
0
XX IO16CONGDLINK PHYS1 PHYS0
PHYS1,0 : PHYSICAL LAYER INTERFACE
0
0
AUTO DETECT
0
1
Reserved
1
0
10Base5
1
1
10BaseT
In auto detect mode. For TC3299A, MA10 open for 10BaseT or 10Base5 auto-detect.
GDLINK
IO16CON
LINK
XX
: When this bit is high, to disable link test pulse generation and integrity checking.
: When this bit is set high the Controller generates IO16* after REG* and CE1* active. If low
this output is generated only on address decode.
: When this bit is high, link test integrity checking is Goood. Otherwise, indicate link signal Loss.
: Reserved.
Configuration Register C
Can be load data from EEPROM only
7
6
5
4
3
2
1
0
XX
XX
XX
XX
XX
XX CRDASEL XX
CRDASEL : When this bit is high. CRDA0, CRDA1 increasing address control by internal cache
state machine.
Confidential.
Copyright © 2003, IC Plus Corp.
11/26
August 27, 20003
TC3299A-DS-R30