TC3299A Datasheet, PDF (12/26 Pages) List of Unclassifed Manufacturers – Ethernet PCMCIA Controller + COMBO Transceiver

TC3299A
Preliminary Data Sheet
When this bit is low, CRDA0, CRDA1 increasing address control by remote read command.
XX
: Reserved.
Hardware Configuration
These functions are configured during a power on RESET.
EECFG(MA9) : MA9 should be pulled down to enable CFGA and CFGB load from EEPROM.
AUICB(MA10) : In media physic auto detect mode. It should be opened for TC3299A.
ENG8(MA11) : If MA11 is pull down and EEPROM 03H bit(0) is setting high, EPCC can work at NE2000 8
bit mode. Otherwise it will work at 16-bit mode.
IOSP(MA12) : If MA12 is pull down, enable I/O base 300H,320H,340H, and 360H separately. If MA12 is
not pulled low, despite of the value of PJ1, 0, TC3299A responses to I/O access at the
I/O base address 300h, 320h, 340h, and 360h.
DCD5BIT(MA13) : Regardless of MA12 setting, once MA13 is pulled down, TC3299A only decodes input
address SA4 - SA0 and can only work at I/O Base address.
Programming Register (R/W)
The EPCC Controller enable software (driver) programming EEPROM or testing interrupt signal through
this register directly. It is located at EPCC's core register Page3 base+02H.
7
6
EESEL XX
5
4
3
2
XX READ CS
SK
1
0
DI DO(r) ATTRDIS
EESEL,CS,SK,DI,DO : The software can read or program serial EEPROM directly through these pins.
EESEL should be set high before starting the EEPROM read/write.
READ
: EPCC can reload CFGA,CFGB and internal PROM if this bit is set high. When
reload state is completed, READ will be cleared to low.
ATTRDIS
: Attribute and common memory access will be disable if it is programmed to high.
NOTE
: DO
: read only
ATTRDIS : write only
3.1 EPCC Core Registers
All registers are 8-bit wide and mapped into two pages which are selected in the Command Registers
(PS0,PS1). Pins A0-A3 are used to address registers within each page. Page 0 register are those
registers which are commonly accessed during EPCC Controller operation while Page 1 registers are
used primarily for initialization. The registers are partitioned to avoid having to perform two read/write
cycles to access commonly used registers.
Register Assignments:
A0-A3
RD
Page 0 Address Assignments (PS1=0,PS0=0)
00H Command (CR)
01H Current Local DMA
Address 0 (CLDA0)
02H Current Local DMA
Address 1 (CLDA1)
03H Boundary Pointer
(BNRY)
WR
Command (CR)
Page Start Register
(PSTART)
Page Stop Register
(PSTOP)
Boundary Pointer
(BNRY)
Confidential.
Copyright © 2003, IC Plus Corp.
12/26
August 27, 20003
TC3299A-DS-R30