TC3299A Datasheet, PDF(18/26 Page) List of Unclassifed Manufacturers – Ethernet PCMCIA Controller + COMBO Transceiver

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

TC3299A Datasheet, PDF (18/26 Pages) List of Unclassifed Manufacturers – Ethernet PCMCIA Controller + COMBO Transceiver

◁

TC3299A

Preliminary Data Sheet

CDH

CD Heartbeat: Failure of the transceiver to transmit a collision signal after

transmission of a packet will set this bit. The Collision Detect (CD) heartbeat

signal must commence during the first 6.4us of the Interframe Gap following

a transmission. In certain collisions, the CD Heartbeat bit will be set even

though the transceiver is not performing the CD heartbeat test.

OWC

Out of Window Collision: Indicates that a collision occurred after a slot

time (51.2us). Transmissions rescheduled as in normal collisions.

Receive Configuration Register (RCR)

This register determines operation of the EPCC during reception of a packet and is used to program what

types of packets to accept.

MON PRO

SEP

Bit

Symbol

Description

SEP

Save Errored Packets

0: Packets with receive errors are rejected.

1: Packets with receive errors are accepted. Receive errors are CRC and

Frame Alignment errors.

Accept Runt Packets

0: Packets with fewer than 64 bytes rejected.

1: Packets with fewer than 64 bytes accepted.

Accept Broadcast

0: Packets with all 1's broadcast destination address rejected.

1: Packets with all 1's broadcast destination address accepted.

Accept Multicast

0: Packets with multicast destination address not checked.

1: Packets with multicast destination address checked.

PRO

Promiscuous Physical

0: Physical address of node must match the station address

programmed in PAR0-PAR5. (Physical address checked)

1: All packets with any physical address accepted. (physical address not

checked)

MON

Monitor Mode: Enables the receiver to check addresses and CRC on

incoming packets without buffering to memory. The missed packet Tally

counter will be incremented for each recognized packet.

0: Packets buffered to memory.

1: Packets checked for address match, good CRC and frame Alignment

but not buffered to memory.

Reserved

Note: D2 and D3 are âOR'dâ together, i.e., if D2 and D3 are set the EPCC will accept broadcast and

multicast addresses as well as its own physical address. To establish full promiscuous (non

discrimination) mode, bits D2, D3 and D4 should be set. In addition the multicast hashing array

must be set to all 1's in order to accept all multicast addresses.

Receive Status Register (RSR)

Confidential.

18/26

August 27, 20003

TC3299A-DS-R30

▷