SD1200 Datasheet, PDF (26/35 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA/SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1200
PRELIMINARY DATA SHEET
Res2 threshold
Res3 threshold
Res4 threshold
Res5 threshold
Res6 threshold
Mode 640x350
Sync Polarity
Mode 640x400
Sync Polarity
Mode 720x400
Sync Polarity
Mode 640x480
Sync Polarity
Mode 800x600
Sync Polarity
Mode 1024x768
Sync Polarity
Mode 1280x1024
Sync Polarity
Maximum VBP
PWM unit delay
Maximum link off
time
Maximum refresh
rate
Maximum input
frequency
Scale factor CE
Scale factor CO
Scale factor NE
and lower bound for 720x400
10 128H-129H Upper bound of the line number for 720x400 mode,
and lower bound for 640x480
10 12AH-12BH Upper bound of the line number for 640x480 mode,
and lower bound for 800x600
10 12CH-12DH Upper bound of the line number for 800x600 mode,
and lower bound for 1024x768
10 12EH-12FH Upper bound of the line number for 1024x768 mode,
and lower bound for 1280x1024
10 130H-131H Upper bound of the line number for 1280x1024 mode.
If the input has more line than this threshold, it is
considered INVALID mode
2
132H[1:0] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
132H[3:2] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
132H[5:4] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
132H[7:6] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
133H[1:0] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
133H[3:2] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
2
133H[5:4] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
8
134H The maximum vertical back porch for input video
13 135H-136H The unit delay used in the external PWM delay
circuitry. If the free-running clock is 1MHz, and the
intended unit delay is 0.2 ns (= 5,000MHz), then a
value of 5,000MHz/1MHz = 5,000 is used here.
22 137H-139H Maximum time when input VSYNC is off before the
LINK_DWN pin turns ON (unit: clock period of the
free running clock). If the free-running clock is
1MHz, and the intended maximum time is 1 second,
then a value of 1,000,000 us/ 1 us = 1,000,000 is used
here.
16 13AH-13BH Maximum refresh rate supported by the LCD panel
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
8
13CH Maximum source clock rate supported by the SD1200
(unit: frequency of free-running clock)
If the intended maximum clock rate is 60MHz, and
the free-running clock is 1MHz, then a value of 60 is
used here.
If the input signal has a higher frequency than this
value, the VCLK0_X status bit will turn ON.
8
13DH Scale factor used when generate look up table for
current even pixel multiplication
8
13EH Scale factor used when generate look up table for
current odd pixel multiplication
8
13FH Scale factor used when generate look up table for next
even pixel multiplication
September, 1998
SmartASIC Confidential
26