SD1200 Datasheet, PDF (13/35 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA/SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1200
PRELIMINARY DATA SHEET
B_OUT3_E
94
B_OUT4_E
95
B_OUT5_E
96
B_OUT6_E
97
B_OUT7_E
99
B_OUT0_O
101
B_OUT1_O
102
B_OUT2_O
103
B_OUT3_O
104
B_OUT4_O
106
B_OUT5_O
107
B_OUT6_O
108
B_OUT7_O
109
HSYNC_O
46
VSYNC_O
47
DCLK_OUT
48
DE_OUT
49
FCLK0
42
VCLK0
43
FCLK1
44
VCLK1
45
ROM_SCL
20
ROM_SDA
21
CPU_SCL
23
CPU_SDA
24
PWM_CTL
25
CLK_1M
26
CLK_1M_O
28
RESET_B
29
HSYNC_X
39
VSYNC_X
40
R_OSD
30
G_OSD
31
B_OSD
32
EN_OSD
33
SCAN_EN
34
TEST_H
36
3.3
O Output Color Blue Even Pixel
3.3
O Output Color Blue Even Pixel
3.3
O Output Color Blue Even Pixel
3.3
O Output Color Blue Even Pixel
3.3
O Output Color Blue Even Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output Color Blue Odd Pixel
3.3
O Output HSYNC
3.3
O Output VSYNC
3.3
O Output Clock to Control Panel
3.3
O Output Display Enable for Panel (active
HIGH)
5
O Input PLL Feedback Clock
5
I Input PLL Output Clock
5
O Output PLL Feedback Clock
5
I Output PLL Output Clock
5
O SCL in I²C for EEPROM interface
5
I/O SDA in I²C for EEPROM interface
5
I SCL in I²C for CPU interface
5
I/O SDA in I²C for CPU interface
5
O PWM control signal (Detail description in
PWM Operation Section)
5
I Free Running Clock (default: 1MHz)
5
O Feedback of free Running Clock
5
I System Reset ( active LOW)
5
O Default HSYNC generated by ASIC (active
LOW)
5
O Default VSYNC generated by ASIC (active
LOW)
5
I OSD Color Red
5
I OSD Color Green
5
I OSD Color Blue
5
I OSD Mixer Enable
=0, No OSD output
=1,R_OUT[7:0]= {R_OSD repeat 8 times}
G_OUT[7:0]= {G_OSD repeat 8 times }
B_OUT[7:0]= {B_OSD repeat 8 times }
5
1 Manufacturing test pin (NC)
5
I Manufacturing test pin (NC)
September, 1998
SmartASIC Confidential
13