SD1200 Datasheet, PDF (16/35 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA/SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1200
PRELIMINARY DATA SHEET
automatically detects polarity of input synchronization and the sizes of back porch,
valid data window and the synchronization pulse width in both vertical and horizontal
directions. The size information is then used not only to decide the input resolution, to
generate the frequency divider for the input PLL, to lock the PLL output clock with
HSYNC, but also to automatically scale the image to full screen, and to synchronize
the output signal with the input signal.
The detection logic is always active to automatically detect any changes to the input
mode. Users can manually change the input mode information at run time through the
CPU interface. Detail operation of the CPU interface is described in Section. “CPU
Interface”.
3.1.3.
Auto calibration
The SD1200 can automatically calibrate the phase of the sample clock in order to
preserve the bandwidth of input signal and get the best quality. The SD1200
implements a proprietary image quality function. During auto-calibration process, the
SD1200 continues search for the best phase to optimize the image quality.
The output image may display some jitter and blurring during the auto-calibration
process, and the image will become crisp and sharp once the optimum phase is found.
User can change the sampling clock phase value by the external CPU. Detail
operation of the CPU interface is described in Section. “CPU Interface”.
The auto calibration process can be delayed and even disabled by the external CPU if
system designer wants to have his/her own implementation.
3.1.4.
PWM operation
The SD1200 implements a very unique algorithm to adjust the phase of the A/D
converter’s sampling clock. An external delay circuitry is required to compliment the
SD1200 for the auto-calibration process. The SD1200 generates a Pulse-Width
Modulated (PWM) signal to the external delay circuitry. The delay circuitry should
insert a certain amount of time delay synchronization pulse based upon the width of
the PWM signal. A brief circuit diagram for the PWM is shown in Figure 3.
The PWM signal from the SD1200 is a periodical signal with a period that is 511
September, 1998
SmartASIC Confidential
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