SD1200 Datasheet, PDF (17/35 Pages) List of Unclassifed Manufacturers – Analog-Interface XGA/SXGA TFT LCD Display Controller

SmartASIC, Inc.
SD1200
PRELIMINARY DATA SHEET
times of the period of the free-running clock connected to the pin “CLK_1M”.
System manufacturers may select any frequency for the free running clock. The
default clock frequency is 1MHz. System manufacturers also decide the unit delay for
the external delay circuitry. The delay information is stored in the EEPROM. When
the SD1200 wants to delay the synchronization pulse for N units of delay, it will
output the PWM with the high time equal to (N * the period of the free-running clock),
and with low time equal to (511-N)* the period of the free-running clock. When
N=511, the PWM signal stays high all the time, and when N=0, the PWM signal is
always low.
Figure 3: SD1200 PWM circuitry block diagram
SD1200
Synchronization pulse
PWM
Delay
Circuitry
Ref_Clk
PLL
3.1.5.
Free Running Clock
As described in previous section, a free-running clock is needed for the SD1200. This
clock is used for many of the SD1200’s internal operations. PWM operation is one of
them. System manufacturers can select the frequency of the free-running clock, and
the default clock frequency is 1MHz. System manufacturer can use an oscillator to
generate the free-running clock, and feed that clock directly to the pin “CLK_1M”, or
use a crystal connecting to “CLK_1M” and “CLK_1M_O”.
September, 1998
SmartASIC Confidential
17