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| SBN0064G Datasheet, PDF (25/37 Pages) List of Unclassifed Manufacturers – Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory | |||
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Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
12 DC CHARACTERISTICS
Table 22 DC Characteristics
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = â20 to +75 °C.
SYMBOL
VDD
VNEG
VLCD
VIL
VIH
VOL
VOH
ILKG
ISTBY
IDD(1)
IDD(2)
Cin
RON
PARAMETER
CONDITIONS
Supply voltage for logic
VNEG=VDD-VEE
LCD bias voltage VLCD= V0(VDD)-V5
LOW level input voltage
Note 1.
For all inputs
HIGH level input voltage
For all inputs
LOW level output voltage of DB0~7
at IOL=1.6 mA.
HIGH level output voltage of DB0~7
at IOH=-200µA.
Leakage current of input pins
for all inputs
Stand-by current at VDD=5 volts
Operating current for display-only
operation
Note 2
Note 3
Operating current for display and
microcontroller access at
tCYC=1 MHz
Input capacitance of all input pins
Note 4
LCD driver ON resistance
Note 5
MIN.
2.7
0
VDD-2.2
0.0
VDD â 0.3
TYP.
5.0
5.0
5.0
MAX.
5.5
16
13
0.8
VDD
0.3
UNIT
V
V
V
V
V
V
VDD
V
0.2
µA
3.0
µA
100
µA
500
µA
8.0
pF
7.5
Îâ¦
Notes:
1. LCD bias voltage VLCD is V0 - V5. V0 should always be connected to VDD.
2. Conditions for the measurement: CLK1=CLK2=VDD, measured at the VDD pin.
3. This value is measured when the microcontroller does not perform any READ/WRITE operation to the chip and the
chip is only performing display operation, with the following condition: 1/64 duty, FCLK1,CLK2=250 KHz,
frame frequency= 70Hz, and no loading for SEG0~63.
4. This values is measured when the microcontroller continuously performs READ/WRITE operation to the chip and the
chip is also performing display operation with the following condition: 1/64 duty, FCLK1,CLK2=250 KHz,
frame frequency= 70Hz, and no loading for SEG0~63.
5. This measurement is for the transmission high-voltage PMOS or NMOS of SEG0~SEG63. Please refer to Section 16
for these driver circuit. The measurement is for the case when the voltage differential between the source and the
drain of the high voltage PMOS or NMOS is 0.1 volts.
2005 May 20
25 of 37
data sheet (v3)
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