OV6620 Datasheet, PDF (25/31 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

OMNIVISION TECHNOLOGIES, Inc.
Advanced Information
Preliminary
OV6620/OV6120
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Therefore, the OV6620/OV6120 sensor takes the read
subaddress from the previous write cycle. In multi-byte
write or multi-byte read cycles, the subaddress is auto-
matically increment after the first data byte so that con-
tinuous locations can be accessed in one bus cycle. A
multi-byte cycle overwrites its original subaddress;
therefore, if a read cycle immediately follows a multi-
Table 15. Slave ID Addresses
byte cycle, you must insert a single byte write cycle that
provides a new subaddress.
The OV6620/OV6120 imager can be programmed to
one-of-eight slave ID addresses. Function pins CS[2:0]
pins 35, 37, 34, respectively).
CS[2:0]
000 001 010 011 100 101 110 111
WRITE ID (hex)
C0
C4
C8
CC
D0
D4
D8
DC
READ ID (hex)
C1
C5
C9
CD
D1
D5
D9
DD
The OV6620/OV6120 sensors support both single chip
and multiple chip configurations. By asserting MULT
(pin 47) high, the sensor can be programmed for up to
8 slave ID addresses. Asserting MULT low configures
the OV6620/OV6120 imagers for single ID slave ad-
dress with address C0 for writes and address C1 for
reads. MULT is internally defaulted to a low condition.
In the write cycle, the second byte in I²C bus is the sub-
address for selecting the individual on-chip registers,
and the third byte is the data associated with this regis-
ter. Writing to unimplemented subaddress is ignored.
In the read cycle, the second byte is the data associ-
ated with the previous stored subaddress. Reading of
unimplemented subaddress returns unknown.
3.2 Register Set
The table below provides a list and description of avail-
able I²C registers contained in the OV6620/OV6120
image sensor.
Table 16. I²C Registers
Subad-
dress
(hex)
Register
00
Gain[6:0]
01
Blue[7:0]
02
Red[7:0]
03
Sat
04
Rsvd04
05
Cnt
06
Brt
07
Sharpness
08
Rsvd08
09
Rsvd09
0A
Rsvd0A
0B
Rsvd0B
Default
(hex)
Read/
Write
Descriptions
AGC Gain Control
GC[7:6] - unimplemented bit, returns ‘X’ when read.
00
RW
GC[5:0] – Storage for the current AGC Gain setting.
This register is updated automatically. If AGC is enabled, the internal control stores the optimal
gain value in this register. IF AGC is not enabled, a “00” is stored in this register.
Blue Gain Control
80
RW
BLU[7] – “0” decrease gain, “1” increase gain.
BLU[6:0] – blue channel gain balance value.
Red Gain Control
80
RW
RED[7] – “0” decrease gain, “1” increase gain.
RED[6:0] – red channel balance value.
80
RW
Saturation Control
SAT[7:0] – saturation adjustment. “FFh”- highest, “00h”-lowest
XX
-
reserved
48
RW
Contrast Control
CTR[7:0] – contrast adjustment. “FFh”-highest, “00h”-lowest
80
RW
Brightness Control
BRT[7:0] – brightness adjustment. “FFh”-highest,“00h”-lowest
Sharpness Control
C6
RW
SHP[7:4] – Threshold of sharpness. Range: 0~80mV, Step: 5 mV
SHP[3:0] – Sharpness control. Range: 0 ~ 8x, Step: 0.5x
XX
-
reserved
XX
-
reserved
XX
-
reserved
XX
-
reserved
14 May 1999
Version 1.11
25