OV6620 Datasheet, PDF (24/31 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

OMNIVISION TECHNOLOGIES, Inc.
Advanced Information
Preliminary
OV6620/OV6120
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
3.1 I²C Bus Protocol Format
In I²C operation, the master must perform the following
operations:
n Generate the start/stop condition
n Provide the serial clock on SCL
n Place the 7-bit slave address, the RW bit,
and the 8-bit subaddress on SDA
The receiver must pull down SDA during the acknowl-
edge bit time. During the write cycle, the OV6620/
OV6120 device returns the acknowledgment and, dur-
ing read cycle, the master returns the acknowledgment
except when the read data is the last byte. If the read
data is the last byte, the master does not perform an
acknowledge, indicating to the slave that the read cycle
can be terminated. Note that the restart feature is not
supported here.
Within each byte, MSB is always transferred first.
Read/write control bit is the LSB of the first byte.
Standard I²C communications require only two pins:
SCL and SDA. SDA is configured as open drain for bi-
directional purpose. A HIGH to LOW transition on the
SDA while SCL is HIGH indicates a START condition. A
LOW to HIGH transition on the SDA while SCL is HIGH
indicates a STOP condition. Only a master can gener-
ate START/STOP conditions.
Except for these two special conditions, the protocol
that SDA remain stable during the HIGH period of the
clock, SCL. Each bit is allowed to change state only
when SCL is LOW (See Figure 9. Bit Transfer on the
I²C Bus and Figure 10. Data Transfer on the I²C Bus
below).
The OV6620/OV6120 I²C supports multi-byte write and
multi-byte read. The master must supply the subad-
dress. in the write cycle, but not in the read cycle.
SDA
SCL
DATA
STABLE
DATA
CHANGE
ALLOWED
I
SDA
Figure 9. Bit Transfer on the I²C Bus
RW
SLAVE ID
SUB ADD
DATA
A
A
A
SCL
S
P
Figure 10. Data Transfer on the I²C Bus
24
Version 1.11
14 May 1999