GS820E32T Datasheet, PDF (18/23 Pages) List of Unclassifed Manufacturers – 2M Synchronous Burst SRAM

GS820E32T/Q-150/138/133/117/100/66
Pipelined DCD Read-Write Cycle Timing
CK
ADSP
Single Read
Single Write
tKL
Burst Read
tS tH
tKH
tKC
ADSP is blocked by E1 inactive
tS tH _{ADSC initiated read}
ADSC
tS tH
ADV
A0-An
GW
tS _tH
RD1
tS tH
tS
WR1
RD2
tH
BW
BA - BD
E1
E2
E3
tS tH
tS tH
tS tH
tS tH
WR1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
tOE tOHZ
Deselected with E3
G
Hi-Z
DQA - DQD
tKQ
Q1A
tS tH
D1A
Q2A
Q2B
Q2C Q2D
Rev: 1.03 2/2000
18/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
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