GS820E32T Datasheet, PDF (14/23 Pages) List of Unclassifed Manufacturers – 2M Synchronous Burst SRAM

Write Cycle Timing
GS820E32T/Q-150/138/133/117/100/66
CK
ADSP
ADSC
ADV
A0-An
GW
BW
BA - BD
E1
E2
E3
G
DQA - DQD
Single Write
Burst Write
Write
Deselected
tS tH
tS tH
tKH tKL ^{tKC ADSP is blocked by E1 inactive}
ADSC initiated write
tS tH
tS tH ^{ADV must be inactive for ADSP Write}
WR1
WR2
WR3
tS tH
tS tH
tS tH
tS tH
WWRR11
WR2
E1 masks ADSP
WWRR33
tS tH
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
Hi-Z
tS _tH
D1A
Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A
D2B
D2C
D2D
D3A
Rev: 1.03 2/2000
14/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
D