SIS5595 Datasheet, PDF (141/216 Pages) List of Unclassifed Manufacturers – Pentium PCI System I/O Chipset

SiS5595 PCI System I/O Chipset
10
R/W RTC Status (RTC_STS)
This bit is set when the RTC generates an alarm or set by a
specific programming sequenc to APCI register 38h and 39h.
While both RTC_EN bit and RTC_STS bit are set, a power
management event is raised(SCI, SMI# or WAKE event). This bit
is only set by hardware and only reset by software writing a “1”
to this bit position.
9
RO Reserved.
8
R/W Power Button Status (PWRBTN_STS)
This bit is set when the power button is pressed (the PWRBT#
signal is asserted Low) or set by a specific programming
sequenc to APCI register 38h and 39h. In the working state,
while both PWRBTN_STS bit and PWRBTN_EN bit are set,then
a SCI or SMI# is raised. In the sleeping state, while
PWRBTN_STS bit is set then a WAKE event is generated. This
bit is only set by hardware and can only be reset by software
writing a “1” to this bit position.
7:6
RO Reserved.
5
R/W Global Status (GBL_STS)
This bit is set by a BIOS-initiated SCI. BIOS can initiate a SCI by
programming Register 13h bit 1 to 1.
4
R/W Bus Master Status(BM_STS)
This is the bus master status bit. This bit is set when a system
bus master is requesting the system bus, and can only be
cleared by writing a “1” to this bit position.
3:1
RO Reserved
0
R/W Power Management Timer Status (TMR_STS)
Power management timer status or DOZE timer status. The free
running timer will be DOZE timer when the Offset Register 2A bit
9 is set to 1 and SCI_EN bit is set to 0. It will be the power
management timer otherwise. If the most significant bit of the 24-
bit timer is changed from '1' to '0' or '0' to '1', then the TMR_STS
bit will be set. While TMR_STS bit and TMR_EN bit are set, a
power management event (SCI or SMI#) is raised. It can only be
cleared by writing a '1' to this bit position.
Register 02h
Power Management Resume Enable Register(PM1_EN)
Default Value: 0000h
Access: Read/Write
BIT
15:11
ACCESS
RO Reserved
DESCRIPTION
Preliminary V2.0 Nov. 2, 1998
135 Silicon Integrated Systems Corporation