SIS5595 Datasheet, PDF (133/216 Pages) List of Unclassifed Manufacturers – Pentium PCI System I/O Chipset

SiS5595 PCI System I/O Chipset
BIT
ACCESS
DESCRIPTION
7
R/W GPCS0# Mode Control
0 : Input mode
1 : Output mode
6
R/W GPCS0# Input Polarity Control
0 : Active low
1 : Active high
5
R/W GPCS0# Input De-Bounce Filter Control
0 : Disable
1 : Enable
When set to 1, the internal de-bounce circuit for GPCS0# input
is enabled.
4
R/W GPCS0# Output Status Control for GPO mode
0 : Output low
1 : Output high
3
RO GPCS0# Status
This bit reflects the status of GPCS0#.
2:1
R/W GPO/GPCS#/GPCSW# selection
00: GPO
01: GPCS#
10: GPO
11: GPCSW#
When the ISA address fallen in the range defined by Reg.
70h~72h will cause GPCS0# to output low when GPCS#
function is selected.
When IOWC# is active and the ISA address fallen in the range
defined by Reg. 70h~72h will cause GPCS0# to output low
when GPCSW# function is selected.
If GPCSW# is selected, this pin can be used to control an
external 74LS374 TTL to latch the values on SD[7:0]. In this
way, the number of general-purpose outputs can be expanded
to 8.
The GPCS0# have another definition, refer to PMU Reg. 77h
bit 0.
0
R/W GPCS0# and GPCS1# Test Mode
This bit should be programmed to 0 for normal operation.
Register 74 ~ 75h GPCS1# Base Address Register
Default Value : 0000h
Access :
Read/Write
Preliminary V2.0 Nov. 2, 1998
127 Silicon Integrated Systems Corporation