SIS5595 Datasheet, PDF (131/216 Pages) List of Unclassifed Manufacturers – Pentium PCI System I/O Chipset

SiS5595 PCI System I/O Chipset
7
R/W GPCS1# Status
This bit is set when an active input to GPCS1# (GPCS1# in input
mode) or GPCS1# is output-low (GPCS1# in GPCS#/GPCSW#
output mode).
6
R/W EXTSMI# Status
This bit is set when the EXTSMI# is active.
5
R/W Floppy Port Status
This bit is set when I/O access to the ports 3F0-3F7h, 370-377h
or an active DREQ2 occurs.
4
R/W Primary IDE channel Device 1 Status
This bit is set when any of the primary IDE channel device 1
associated ports is accessed.
3
R/W Secondary IDE channel Device 1 Status
This bit is set when any of the secondary IDE channel device 1
associated ports is accessed.
2
R/W APM Status.
This bit is set when a 1 is written to Bit_1 of Reg. 7Ch.
1:0
R/W Reserved.
This bit must be programmed to 0.
Register 68h ~ 69h/6Ah~6Bh
IRQ and NMI Enable for Wake-up 0/1, and System
Standby Timer 0/1 reload event control
Default Value : 0000h
Access :
BIT
15:3
2
1:0
R/W
ACCESS
DESCRIPTION
R/W Correspond to the enable bits for IRQ15-3 to reload the
System Standby Timer 0, 1 or to generate a wake-up event.
0 : Enable
1 : Disable
R/W Corresponds to the enable bits for NMI to reload the System
Standby Timer 0, 1 or to generate wakeup event.
0 : Enable
1 : Disable
R/W Correspond to the enable bits for IRQ1-0 to reload the
System Standby Timer 0, 1 or to generate a wakeup event.
0 : Enable
1 : Disable
Register 6Ch ~ 6Dh IRQ and NMI to Reload System Standby Timer 2 Enable
Default Value : 0000h
Access :
Read/Write
Preliminary V2.0 Nov. 2, 1998
125 Silicon Integrated Systems Corporation