W65C21S Datasheet, PDF (14/16 Pages) List of Unclassifed Manufacturers – Peripheral Interface Adapter (PIA)

The Western Design Center, Inc.
W65C21S Data Sheet
CA1/CB1 CONTROL
CRA (CRB)
BIT 1
BIT 0
ACTIVE TRANSITION OF
INPUT SIGNAL*
IRQAB (IRQBB) INTERRUPT OUTPUTS
0
0
Negative
Disable – remains high
0
1
Negative
Enable – goes low when bit 7 in CRA (CRB) is set by active transition of
signal on CA1 (CB1)
1
0
Positive
Disable – remains high
1
1
Positive
Enable – as explained above
*Note: Bit 7 of CRA (CRB) will be set to a Logic 1 by an active transition of the CA1 (CB1) signal. This is independent of the state of bit 0 in CRA (CRB).
CA2/CB2 INPUT MODES
CRA (CRB)
ACTIVE TRANSITION OF
BIT 5 BIT 4 BIT 3
INPUT SIGNAL*
IRQAB (IRQBB) INTERRUPT OUTPUTS
0
0
0
Negative
Disable – remains high
0
0
1
Negative
Enable – goes low when bit 6 in CRA (CRB) is set by active transition of
signal on CA2 (CB2)
0
1
0
Positive
Disable – remains high
0
1
1
Positive
Enable – as explained above
*Note: Bit 6 of CRA (CRB) will be set to a Logic 1 by an active transition of the CA2 (CB2) signal. This is independent of the state of bit 0 in CRA (CRB).
CRA (CRB)
BIT 5 BIT 4 BIT 3
1
0
0
1
0
1
1
1
0
1
1
1
CA2 OUTPUT MODES
ACTIVE TRANSITION OF
INPUT SIGNAL*
“Handshake on Read”
Pulse Output
Manual Output
Manual Output
IRQAB (IRQBB) INTERRUPT OUTPUTS
CA2 is set high on ac active transition of the CA1 interrupt input signal and
set low by a microprocessor “Read A Data” operation. This allows
positive control of data transfers from the peripheral device to the
microprocessor.
CA2 goes low for one cycle after a microprocessor “Read A Data”
operation. This pulse can be used to signal the peripheral device that data
was taken.
CA2 set low
CA2 set high
CRA (CRB)
BIT 5 BIT 4 BIT 3
1
0
0
1
0
1
1
1
0
1
1
1
CB2 OUTPUT MODES
ACTIVE TRANSITION OF
INPUT SIGNAL*
“Handshake on Read”
Pulse Output
Manual Output
Manual Output
IRQAB (IRQBB) INTERRUPT OUTPUTS
CB2 is set low on microprocessor “Write B Data” and is set high by an
active transition of the CB1 input signal. This allows positive control of
data transfers from the microprocessor to the peripheral device.
CB2 goes low for one cycle after a microprocessor “Write B Data”
operation. This can be used to signal the peripheral device that data is
available.
CB2 set low
CB2 set high
Table 3. Interrupt Input/Peripheral Control Line Operation.
The Western Design Center
W65C21S
14