W65C21S Datasheet, PDF (13/16 Pages) List of Unclassifed Manufacturers – Peripheral Interface Adapter (PIA)

The Western Design Center, Inc.
All output data to a peripheral is stored in the corresponding
Output Register (ORA or IRB). This data is then presented
to the Peripheral Interface Buffer (A and B) and placed on
the respective I/O. Port lines. Writing a “0” into any bit
position of ORA or ORB results in the corresponding
peripheral I/O Port line going low (<0.4V), providing that
particular line is programmed as an output. Writing a “1”
into a bit position results in the corresponding output going
high.
READING THE PERIPHERAL PORT
Performing a Read operation with RS1=0, RS0=0 and the
Data Direction Register Access Control bit (CRA-2) = 1,
directly transfers the data on the Peripheral A I/O lines to the
data bus. In this situation, the data bus will contain both
directly transfers the data on the Peripheral A I/O lines to the
data bus. In this situation, the data bus will contain both
the input and output data. The processor must be
programmed to recognize and interpret only those bits which
are important to particular peripheral operation being
performed.
Since the processor always reads the Peripheral A I/O port
pins instead of the actual Peripheral Output Register (ORA),
it is possible for the data read by the processor to differ from
the contents of the Peripheral Output Register for an output
line. This is true when the I/O pin is not allowed to go to a
full +2.4V DC when the Peripheral Output register contains a
logic 1. In this case, the processor will read a 0 from the
Peripheral A pin, even though the corresponding bit in the
Peripheral Output register is a 1.
READING THE PERIPHERAL B I/O PORT
Reading the Peripheral B I/O port yields a combination of
input and output data in a manner similar to the Peripheral A
port. However, data is read directly from the Peripheral B
Output Register (ORB) for this lines programmed to act as
outputs. It is therefore possible to load down the Peripheral
B Output lines without causing incorrect data to be
transferred back to the processor or Read operation.
REGISTER ACCESS AND SELECTION
W65C21S Data Sheet
The two Register Select lines (RS0, RS1), in conjunction
with the Control Registers (CRA, CRB) Data Direction
Register access bits (see table 1, bit 2) select the various
W65C21S registers to be accessed by the CPU, RS0 and RS1
are normally connected to the microprocessor (CPU) address
output lines. Through control of these lines, the
CPU can write directly into the Control Registers (CRA,
CRB) the Data Direction Registers (DDRA, DDRB) and the
Peripheral Output Registers (ORA, ORB) in addition, the
microprocessor may directly read the contents of the Control
Registers and the Data Direction Registers. Accessing the
Peripheral Output Register for the purpose of reading data
back into the processor operates differently on the ORA and
the ORB registers and therefore is shown separately in Table
2.
CROSS REFERENCE GUIDE
The W65C21S is a replacement part for older PIA devices,
but has several variations.
The Port A input buffers supply 1 TTL load pull-up current
(100uA) at 2.4V when in the input mode and can supply the
same drive current as the Port B buffers when in the output
mode.
A current limiting resistor should be used on the peripheral
port pins (PA0-PA7 and PB0-PB7) when clamping an output.
The Western Design Center
W65C21S
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