W65C21S Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – Peripheral Interface Adapter (PIA)

The Western Design Center, Inc.
SIGNAL DESCRIPTION
The PIA interfaces to the 65xx microprocessor family with a
reset line, a PHI2 clock line, a read/write line, two interrupt
request lines, two register select lines, three chip select lines
and an 8-bit bidirectional data bus.
The PIA interfaces to the peripheral devices with four
interrupt/control lines and two 8-bit bidirectional data buses.
Figures 1 and 2 show the pin assignments for these interface
signals and Figure 4 shows the interface relationship of these
signals as they pertain to the CPU and the peripheral devices.
CHIP SELECT (CS0, CS1, CS2B)
The PIA is selected when CS0 and CS1 are high and CS2B is
low. These three chip select lines are normally connected to
the processor address lines either directly or through external
decoder circuits. When the PIA is selected data will be
transferred between the data lines and PIA registers, and/or
peripheral interface lines as determined by the RWB, RS0
and RS1 lines and the contents of Control Registers A and B.
CLOCK SIGNAL (PHI2)
The Phase 2 Clock Signal (PHI2) is the system clock that
triggers all data transfers between the CPU and the PIA.
PHI2 is generated by the CPU and us therefore the
synchronizing signal between the CPU and the PIA.
DATA BUS (D0-D7)
The eight bidirectional data bus lines are used to transfer data
between the W65C21S and the microprocessor.
During a Read operation, the contents of the W65C21S
internal Data Bus Buffer (DBB) are transferred to the
microprocessor via the Data Bus lines. During a Write
operation, the Data Bus lines represent high impedance
inputs over which data is transferred from the microprocessor
to the Data Input Register (DIR). The Data
Bus lines are in the high impedance state when the W65C21S
is unselected.
INTERRUPT STATUS CONTROL – CA1, CA2 (Port A)
and CB1, CB2 (Port B)
The two Interrupt Status Control lines for each Data Port are
controlled by the Interrupt Status Control logic (A and B).
This logic interprets the contents of the corresponding
Control Register (CRA and CRB), allowing the Interrupt
Status Control lines to perform various peripheral control
functions.
PERIPHERAL DATA PORT A (PA0-PA7)
Peripheral Data Port A is an 8-line, bidirectional bus used for
the transfer of data, control and status information between
the W65C21S and a peripheral device. Each data port bus
line may be individually programmed as either an input or
output under control of the Data Direction Register (DDRA).
W65C21S Data Sheet
Data flow direction may be selected on a line-by-line basis
with intermixed input and output lines within the same port.
PERIPHERAL DATA PORT B (PA0-PA7)
Peripheral Data Port B is an 8-line, bidirectional bus used for
the transfer of data, control and status information between
the W65C21S and a peripheral device. Functional operation
is identical to Peripheral Data Port A, thus allowing the
W65C21S to independently control two peripheral devices.
READ/WRITE SIGNAL (RWB)
Read/Write (RWB) controls the direction of data transfers
between the PIA and the data lines associated with the CPU
and the peripheral devices. A high on the RWB line permits
the peripheral devices to transfer data to the CPU from the
PIA. A low on the RWB line allows data to be transferred
from the CPU to the peripheral devices from the PIA.
REGISTER SELECT (RS0, RS1)
The Register Select inputs allow the microprocessor to select
the W65C21S internal registers as presented Table 2. Full
functionality is described under the Functional Description
section for Register Access and Selection.
RESET SIGNAL (RESB)
A low signal (Logic 0) on the Reset line serves to initialize
the W65C21S, clearing all internal registers (to Logic 0) and
placing all peripheral interface lines (PA and PB) in the input
state.
FUNCTIONAL DESCRIPTION
The W65C21S PIA is organized into two independent
sections referred to as the A Side and the B Side. Each
section consists of Control Register (CRA, CRB), Data
Direction Register (DDRA, DDRB), Output Register (ORA,
ORB), Interrupt Status Control (ISCA, ISCB) and the buffers
necessary to drive the Peripheral Interface buses.
Data Bus Buffers (DBB) interface data from the two sections
to the data bus, while the Date Input Register (DIR)
interfaces data from the DBB to the PIA registers. Chip
Select and RWB control circuitry interface to the processor
bus control lines. Figure 3 is a block diagram of the
W65C21S PIA.
CONTROL REGISTERS (CRA AND CRB)
Table 1 illustrates the bit designation and functions in the two
control registers. The individual control registers allow the
microprocessor to control the operation of the Interrupt
Control inputs (CA1, CA2, CB1, CB2), and Peripheral
Control outputs (CA2, CB2). Bit 2 in each register controls
the addressing of the Data Direction Registers (DDRA,
DDRB) and the Output Registers (ORA, ORB). In addition,
two bits (bit 6 and 7) in each control register indicate the
status of the Interrupt Status Control input lines (CA1, CA2,
CB1, CB2). These Interrupt Status bits (IRQA1, IRQA2 or
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W65C21S
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