W65C21S Datasheet, PDF (11/16 Pages) List of Unclassifed Manufacturers – Peripheral Interface Adapter (PIA)

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IRQB1, IRQB2) are normally interrogated by the
microprocessor during the interrupt service routine to
determine the source of an active interrupt. These two
interrupt lines drive the interrupt input (IRQB or NMIB) of
the microprocessor.
DATA BUS BUFFERS (DBB)
The Data Bus Buffers are 8-bit bidirectional buffers used for
data exchange, on the D0-D7 Data Bus, between the
microprocessor and the PIA. These buffers are tri-state and
are capable of driving a two TTL load (when operating in an
output mode.
DATA DIRECTION REGISTERS (DDRA, DDRB)
The Data Direction Registers (DDRA, DDRB) allow the
processor to program each line in the 8-bit Peripheral I/O
port to be either an input or an output. Each bit in DDRA
controls the corresponding line in the Peripheral A port and
each bit in DDRB controls the corresponding line in the
Peripheral B port. Writing a “0” in a bit position in the Data
Direction Register causes the corresponding Peripheral I/O
line to act as in input; a “1” results in the line being an
output.
Bit 2 (DDRA, DDRB) in each Control Register (CRA and
CRB) controls the accessing to the Data Direction Register or
the Peripheral interface. If bit 2 is a “1”, a Peripheral Output
register (ORA, ORB) is selected, and if bit 2 is a “0”, a Data
Direction Register (DDRA, DDRB) is selected. The Data
Direction Register Access Control bit, together with the
Register Select lines (RS0, RS1) selects the various internal
registers as shown in Table 2.
In order to write data into DDRA, ORA, DDRB or ORB
registers, bit 2 in the proper Control Register must first be
set. The desired register may then be accessed with the
address determined by the address interconnect technique
used.
DATA INPUT REGISTER (DIR)
During a Write data operation, the microprocessor writes data
into the W65C21S by placing data on the Data Bus. This
data is then latched into the Data Input Register by the Phase
Two (PHI2) clock. Once in the DIR, this data byte is
transferred into one of six internal registers. This data
transfer occurs after the trailing edge of the PHI2 clock pulse
that latched the data into the DIR. This timing delay
guarantees the data on the peripheral output lines (PA or PB)
will make a smooth transition from low to high or high to
low, and the output voltage will remain stable when there is
to be no change in polarity.
INTERRUPT INPUT/PERIPHERAL CONTROL LINES
(CA1, CA2, CB1, CB2)
The four interrupt input/peripheral control lines provide a
number of special control functions. These lines greatly
enhance the power of the two general purpose interface ports
(PA0-PA7, PB0-PB7). Figure 5 summarizes the operation of
these control lines.
W65C21S Data Sheet
CA1 is an interrupt input only. An active transition of the
signal on this input will set bit 7 of the Control Register A to
a logic 1. The active transition can be programmed by
setting a “0” in bit 1 of the CRA if the interrupt flag (bit7 of
CRA) is to be set on a negative transition of the CA1 signal
or a “1” if it is to be set on a positive transition
NOTE:
A negative transition is defined as a transition from a high to
a low and a positive transition is defined as a transition from
a low to a high voltage.
CA2 can act as a totally independent interrupt or as a
peripheral control output. As an input (CRA, bit 5=0) it acts
to set the interrupt flag, bit 6 of CRA, to a logic on 1 on the
active transition selected by bit 4 of CRA.
These control register bits and interrupt inputs serve the same
basic function as that described above for CA1. The input
signal sets the interrupt flag which serves as the link between
the peripheral device and the processor interrupt structure.
The interrupt disable bits allows the processor to exercise
control over the system interrupt.
In the output mode (CRA, bit 5=1), CA2 can operate
independently to generate a simple pulse each time the
microprocessor is selected by setting CRA bit 4 to a 0 and
CRA bit 3 to a 1. This pulse output can be used to control
the counters, shift registers, etc., which make sequential data
available on the Peripheral input lines.
A second output mode allows CA2 to be used in conjunction
with CA1 to “handshake” between the processor and the
peripheral device. On the A side, this technique allows
positive control of data transfers from the peripheral device
into the microprocessor. The CA1 input signals the
processor that data is available by interrupting the processor.
The processor reads the data and sets CA2 low. This signals
the peripheral device that it can make new data available.
The final output mode can be selected by setting bit 4 of
CRA to a 1. In this mode, CA2 is a simple peripheral control
output that can be set high or low by setting bit 3 of CRA to a
1 or a 0 respectively.
CB1 operates as an interrupt input only in the same manner
as CA1. Bit 7 of CRB is set by the active transition selected
by bit 0 of CRB. Likewise, the CB2 input mode operates
exactly the same as the CA2 input modes. The CB2 output
modes, CRB bit 5=1, differ somewhat from those of CA2.
The pulse output occurs when the processor writes data into
the Peripheral B Output Register. Also, the “handshaking”
operates on data transfers from the processor into the
peripheral device.
INTERRUPT REQUEST (IRQAB, IRQBB)
The active low Interrupt Request lines (IRQAB and IRQBB)
act to interrupt the microprocessor either directly or through
external interrupt priority circuitry. These lines are open
drain and are capable of sinking 3.2 milliamps from an
external source. This permits all interrupt request lines to be
tied together in a wired OR configuration. The A and B in
the titles of these lines correspond to the peripheral port B so
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W65C21S
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