M13S128168A-2N Datasheet, PDF (7/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
IDD Specifications
Symbol
-4
IDD0
90
IDD1
110
IDD2P
8
IDD2F
40
IDD2Q
40
IDD3P
20
IDD3N
70
IDD4R
190
IDD4W
160
IDD5
180
IDD6
3
IDD7
250
Version
-5
80
100
8
35
35
15
65
170
150
160
3
230
M13S128168A (2N)
Automotive Grade
Unit
-6
70
mA
90
mA
8
mA
30
mA
30
mA
15
mA
60
mA
150
mA
140
mA
140
mA
3
mA
210
mA
Input / Output Capacitance
Parameter
Package Symbol
Min
Max
Delta Cap
(max)
Unit Note
Input capacitance (A0~A11, BA0~BA1, _TSOP
CKE, CS , RAS , CAS , WE )
BGA
C_IN1
1.5
TBD
5
TBD
pF
0.5
1,4
pF
Input capacitance (CLK, CLK )
TSOP
C_IN2
BGA
1.5
TBD
5
TBD
pF
0.25
1,4
pF
Data & DQS input/output capacitance
TSOP
BGA
C_OUT
1.5
TBD
5
TBD
pF
0.5
1,2,3,4
pF
Input capacitance (DM)
TSOP
BGA
C_IN3
1.5
TBD
5
TBD
pF
0.5
1,2,3,4
pF
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. V_DDQ = 2.5V ± 0.2V, V_DD = 2.5V ± 0.2V. For all devices, f=100MHz, T_A =25°C, V_OUT(DC) =
V_DDQ/2, V_OUT (peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in
loading (to facilitate trace matching at the board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1
7/49