M13S128168A-2N Datasheet, PDF (48/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Revision History
Revision
1.0
1.1
Date
2012.10.29
2013.03.04
M13S128168A (2N)
Automotive Grade
Description
Original
Delete CAS Latency:2
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1
48/49