M13S128168A-2N Datasheet, PDF (36/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
Write followed by Precharge (@ BL=4)
0
1
CLK
CLK
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
BA0,BA1
BAa
A10/AP
ADDR
Ca
(A0~An)
WE
DQS
BAa
tWR
DQ
DM
COMMAND
Da0 Da1 Da2 Da3
WRITE
PRE
CHARGE
M13S128168A (2N)
Automotive Grade
7
8
9
10
: Don’t care
10122B16R.B
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1
36/49