M13S128168A-2N Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – Double-data-rate architecture, two data transfers per clock cycle

ESMT
M13S128168A (2N)
Automotive Grade
DDR SDRAM
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
 Double-data-rate architecture, two data transfers per clock cycle
 Bi-directional data strobe (DQS)
 Differential clock inputs (CLK and CLK )
 DLL aligns DQ and DQS transition with CLK transition
 Four bank operation
 CAS Latency : 2.5, 3, 4
 Burst Type : Sequential and Interleave
 Burst Length : 2, 4, 8
 All inputs except data & DM are sampled at the rising edge of the system clock (CLK)
 Data I/O transitions on both edges of data strobe (DQS)
 DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
 Data mask (DM) for write masking only
 V_DD = 2.5V ± 0.2V, V_DDQ = 2.5V ± 0.2V
 15.6us refresh interval for V grade; 3.9us refresh interval for VA grade
 Auto & Self refresh (self refresh is not supported for VA grade)
 2.5V I/O (SSTL_2 compatible)
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2013
Revision : 1.1
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