M12S128324A Datasheet, PDF (7/46 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
M12S128324A
Parameter
Symbol
Col. address to col. address delay tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
CAS latency = 1
Version
-6
-7
1
2
1
0
Unit
Note
CLK
3
ea
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
Parameter
-6
Symbol
-7
Unit
Min Max Min Max
CAS latency = 3
6
7
CLK cycle time
CAS latency = 2
tCC
8 1000 8.6 1000
ns
CAS latency = 1
20
20
CLK to valid
output delay
CAS latency = 3
CAS latency = 2
tSAC
CAS latency = 1
5.8
6
7
7
ns
17
18
CAS latency = 3
2
2
Output data
CAS latency = 2
tOH
2
2
ns
hold time
CAS latency = 1
2
2
CLK high pulsh width
tCH
2
2.5
ns
CLK low pulsh width
tCL
2
2.5
ns
Input setup time
tSS
2
2
ns
Input hold time
tSH
1
1
ns
CLK to output in Low-Z
tSLZ
1
1
ns
CLK to output
in Hi-Z
CAS latency = 3
CAS latency = 2
tSHZ
CAS latency = 1
5.8
6
7
7
ns
17
18
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Note
1
1,2
2
3
3
3
3
2
-
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
7/46