M12S128324A Datasheet, PDF (5/46 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
CAPACITANCE (VDD = 2.5V, TA = 25 °C , f = 1MHZ)
Parameter
Symbol
Min
Input capacitance (A0 ~ A11, BA0 ~ BA1)
CIN1
2
Input capacitance
CIN2
2
(CLK, CKE, CS , RAS , CAS , WE & DQM)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
M12S128324A
Max
Unit
4
pF
4
pF
5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
ICC6
Burst Length = 1
tRC ≥ tRC(min)
IOL = 0 mA
CKE ≤ VIL(max), tcc = 10ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
CKE ≤ VIL(max), tcc = 10ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
Input signals are changed one time during 2clks
All other pins ≥ V_DD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
I_OL = 0 mA
Page Burst
2 Banks activated
tCK = tCK(min)
tRC ≥ tRC(min)
CKE ≤ 0.2V
Version
-6
-7
Unit Note
110 90 ^{mA 1,2}
0.8
mA
0.6
25
mA
7
3
mA
3
30
mA
10
mA
180 160 _{mA 1,2}
180 160 mA
2
mA
Note :
1. Measured with outputs open. Addresses are changed only one time during t_CC(min).
2. Refresh period is 64ms. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posed to
any given SDRAM, and the maximum absolute internal between any AUTO REFRSH command and the next AUTO
REFRESH command is 8x15.6μm. Addresses are changed only one time during t_CC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
5/46