S1D13806 Datasheet, PDF (83/730 Pages) Epson Company – S1D13806 Embedded Memory Display Controller

Epson Research and Development
Vancouver Design Center
Page 77
Sync Timing
FPFRAME
FPLINE
MOD
t1
t2
t3
t4
t5
Data Timing
FPLINE
t6
t9
t7
t10
t8
t11 t12
FPSHIFT
FPDAT[7:0]
Invalid
t13 t14
1
2
Figure 6-27: Dual Monochrome 8-Bit Panel A.C. Timing
Table 6-24 : Dual Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t12
t11
t13
t14
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE pulse width
FPLINE period
MOD transition to FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT rising edge
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
Min
Typ
note 2
12
11
note 3
3
note 5
t10 + 2
4
note 6
note 7
2
2
2
2
Max
note 4
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = LCD pixel clock period. LCD pixel clock frequency is source divided by 1, 2, 3 or 4(see REG[014h]).
2. t1_min = t3_min - 12
3. t3_min = [((REG[032h] bits [6:0]) + 1) × 8 + ((REG[034h] bits [4:0]) + 1) × 8]
4. t5_max = [((REG[034h] bits [4:0]) + 1) × 8 + 3]
5. t6_min = [((REG[034h] bits [4:0]) + 1) × 8 - 18] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 17] for 16 bpp color depth
6. t9_min = [((REG[034h] bits [4:0]) + 1) × 8 - 7] for 4 bpp or 8 bpp color depth
= [((REG[034h] bits [4:0]) + 1) × 8 - 6] for 16 bpp color depth
7. t10_min= 9 for 4 bpp or 8 bpp color depth
= 8 for 16 bpp color depth
Hardware Functional Specification
Issue Date: 02/10/04
S1D13806
X28B-A-001-13