S1D13806 Datasheet, PDF (324/730 Pages) Epson Company – S1D13806 Embedded Memory Display Controller

Page 114
Epson Research and Development
Vancouver Design Center
12.2 Considerations
Software can determine if the MediaPlug interface is enabled or disabled by reading the
Config Status Register (REG[00Ch]) and masking the data with 80h. If the masked result
equals 80h, the MediaPlug Interface is enabled.
The MediaPlug interface requires a source clock between 8MHz and 19MHz to operate
(optimal is 14.318MHz). By default, the MediaPlug software assumes a 14.318MHz
frequency is available on CLKI2. If the frequency of CLKI2 is changed, software should
reprogram the MediaPlug Clock Register (REG[01Ch]) to select a clock source that is
suitable, or program the clock divide bits to obtain a frequency within the correct range.
If the S5U13806B00x evaluation board is used, the clock chip should be programmed to
support a valid clock for the MediaPlug interface. A HAL function is available which
programs the clock chip for the MediaPlug interface.
S1D13806
X28B-G-003-07
Programming Notes and Examples
Issue Date: 02/02/21