S1D13806 Datasheet, PDF (706/730 Pages) Epson Company – S1D13806 Embedded Memory Display Controller

Page 16
Epson Research and Development
Vancouver Design Center
4.5 Register/Memory Mapping
The S1D13806 is a memory-mapped device. The SA-1110 uses the memory assigned to a
chip select (nCS4 in this example) to map the S1D13806 internal registers and display
buffer. The internal registers are mapped in the lower SA-1110 memory address space
starting at zero. The display buffer requires 1.25M bytes and is mapped in the third and
fourth megabytes of the SA-1110 address space (ranging from 20 0000h to 33 FFFFh).
This implementation decodes as shown in the following table.
A21 (M/R#)
0
0
0
1
x = don’t care
Table 4-3: Register/Memory Mapping for Typical Implementation
A20
A12
Address Range
Function
0
0
0 to 1FFh
Control Registers Decoded
0
1
1000h to 1FFFh
MediaPlug Registers Decoded
1
x
10 0000h to 1F FFFFh
BitBLT Registers Decoded
x
x
20 0000h to 33 FFFFh
Display Buffer Decoded
Each chip select on the SA-1110 provides 64M byte of address space. Since the SA-1110
address bits A[25:22] are ignored, the S1D13806 registers and display buffer are aliased
within the allocated address space. If aliasing is undesirable, the address space must be fully
decoded.
S1D13806
X28B-G-012-05
Interfacing to the StrongARM SA-1110 Processor
Issue Date: 01/02/26