S1D13806 Datasheet, PDF (468/730 Pages) Epson Company – S1D13806 Embedded Memory Display Controller

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Epson Research and Development
Vancouver Design Center
“Rotation”=dword:0
“RefreshRate”=dword:3C
“Flags”=dword:2
Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch
= 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When
the display driver starts, it will read these values in the registry and attempt to match a mode
table against them. All values must be present and valid for a match to occur, otherwise the
display driver will default to the FIRST mode table in your list.
A WinCE desktop application (or control panel applet) can change these registry values,
and the display driver will select a different mode upon warmboot. This allows the display
driver to support different display configurations and/or orientations. An example appli-
cation that controls these registry values will be made available upon the next release of the
display driver; preliminary alpha code is available by special request.
• The display driver is CPU independent, allowing use of the driver for several Windows
CE Platform Builder supported platforms.
• By default, the 13806CFG program assumes PCI addressing for the S5U13806B00C
evaluation board. This means that the display driver will automatically locate the
S1D13806 by scanning the PCI bus (currently only supported for the CEPC platform). If
you select the address option “Other” and fill in your own custom addresses for the
registers and video memory, then the display driver will not scan the PCI bus and will
use the specific addresses you have chosen.
• When using the display driver on hardware other than the S5U13806B00C evaluation
board, you must ensure that your hardware provides the correct clock frequencies for
CLKI, CLKI2, and CLKI3. The 13806CFG program defaults CLKI to 25.175MHz,
CLKI2 to 14.318MHz, and CLKI3 to 50.000MHz. The 13806CFG program also
defaults BUSCLK to the PCI clock of 33.333MHz.
On the evaluation board, the display driver will correctly program the clock chip to
support the CLKI and CLKI2 frequencies, and BUSCLK is derived from the PCI clock.
On customer hardware, you must ensure that the clocks you provide to all clock inputs
match the settings you chose in the Clocks tab of the 13806CFG program.
If you run the S1D13806 with a single clock source, make sure your clock sources for
LCD, CRT, MediaPlug, and MCLK are correctly set to use the correct clock input
source (typically BUSCLK). Also ensure that you enable the clock dividers as required
for different display hardware.
S1D13806
X28B-E-001-05
Windows® CE 2.x Display Drivers
Issue Date: 01/05/22