S1D13505 Datasheet, PDF (79/565 Pages) Epson Company – S1D13505 Embedded RANMAC LCD/CRT Controller

Page 74
Epson Research and Development
Vancouver Design Center
7.4 Power Sequencing
7.4.1 LCD Power Sequencing
SUSPEND# or
LCD Enable Bit
LCDPWR
FPFRAME
FPLINE
FPSHIFT
FPDATA
DRDY
CLKI
t1
t2 t3
t4
t5 t6
t7
Figure 7-22: LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity
Table 7-21: LCD Panel Power Off/ Power On
Symbol
Parameter
Min
t1 _{SUSPEND# or LCD ENABLE BIT low to LCDPWR off}
t2 SUSPEND# or LCD ENABLE BIT low to FPFRAME inactive
t3 _{FPFRAME inactive to FPLINE, FPSHIFT, FPDATA, DRDY inactive}
128
t4 SUSPEND# to CLKI inactive
130
t5
SUSPEND# or LCD ENABLE BIT high to FPLINE, FPSHIFT,
FPDATA, DRDY active
t6
FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and
128
FPFRAME active
t7 _{CLKI active to SUSPEND# inactive}
0
Max
2T_FPFRAME +
8T_PCLK
1
T_FPFRAME +
8T_PCLK
Units
ns
Frames
Frames
Frames
ns
Frames
ns
Note
Where T_FPFRAME is the period of FPFRAME and T_PCLK is the period of the pixel clock.
S1D13505
X23A-A-001-14
Hardware Functional Specification
Issue Date: 01/02/02