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S1D13505 Datasheet, PDF (120/565 Pages) Epson Company – S1D13505 Embedded RANMAC LCD/CRT Controller
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Epson Research and Development
Vancouver Design Center
Page 115
bit 4
bits 3-2
RAS#-to-CAS# Delay Value (NRCD)
This bit selects the DRAM RAS#-to-CAS# delay parameter, tRCD. This bit specifies the number
(NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS#
access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
NRCD
= Round-Up((tRAC + 5)/TM - 1)
=2
= Round-Up(tRAC/TM - 1)
= Round-Up(tRAC/TM - 0.45)
if EDO and NRP = 1 or 2
if EDO and NRP = 1.5
if FPM and NRP = 1 or 2
if FPM and NRP = 1.5
Note that for EDO-DRAM and NRP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for
NRCD. This is done to satisfy the CAS# address setup time, tASC.
The resulting tRC is related to NRCD as follows:
tRCD
tRCD
tRCD
tRCD
= (NRCD) TM
= (1.5) TM
= (NRCD + 0.5) TM
= (NRCD) TM
if EDO and NRP = 1 or 2
if EDO and NRP = 1.5
if FPM and NRP = 1 or 2
if FPM and NRP = 1.5
REG[22h] bit 4
0
1
Table 8-13: RAS#-to-CAS# Delay Timing Select
NRCD
2
1
RAS#-to-CAS# Delay (tRCD)
2
1
RAS# Precharge Timing Value (NRP) Bits [1:0]
Minimum Memory Timing for RAS# precharge
These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number
(NRP) of MCLK periods (TM) used to create tRP – see the following formulae. Note, these formulae
assume an MCLK duty cycle of 50 +/- 5%.
NRP
=1
if (tRP/TM) < 1
= 1.5
if 1 ≤ (tRP/TM) < 1.45
=2
if (tRP/TM) ≥ 1.45
The resulting tRC is related to NRP as follows:
tRP
= (NRP + 0.5) TM if FPM refresh cycle and NRP = 1 or 2
tRP
= (NRP) TM
for all other
Hardware Functional Specification
Issue Date: 01/02/02
S1D13505
X23A-A-001-14
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