S1D13505 Datasheet, PDF (127/565 Pages) Epson Company – S1D13505 Embedded RANMAC LCD/CRT Controller

Page 122
Epson Research and Development
Vancouver Design Center
9 Display Buffer
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When
CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below:
Table 9-1: S1D13505 Addressing
CS#
M/R#
Access
Register access:
0
0
• REG[00h] is addressed when AB[5:0] = 0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
0
1
Memory access: the 2M byte display buffer is addressed by
AB[20:0]
1
X
S1D13505 not selected
The display buffer address space is always 2M bytes. However, the physical display buffer may be
either 512K bytes or 2M bytes – see “Summary of Configuration Options”.
The display buffer can contain an image buffer, one or more Ink/Cursor buffers, and a half-frame
buffer.
A 512K byte display buffer is replicated in the 2M byte address space – see the figure below.
512K Byte Buffer
Image Buffer
Ink/Cursor Buffer
Half-Frame Buffer
Image Buffer
Ink/Cursor Buffer
Half-Frame Buffer
Image Buffer
Ink/Cursor Buffer
Half-Frame Buffer
Image Buffer
Ink/Cursor Buffer
Half-Frame Buffer
AB[20:0]
000000h
07FFFFh
080000h
0FFFFFh
100000h
17FFFFh
180000h
1FFFFFh
2M Byte Buffer
Image Buffer
Ink/Cursor Buffer
Half-Frame Buffer
Figure 9-1: Display Buffer Addressing
S1D13505
X23A-A-001-14
Hardware Functional Specification
Issue Date: 01/02/02