S1D13505 Datasheet, PDF (75/565 Pages) Epson Company – S1D13505 Embedded RANMAC LCD/CRT Controller

Page 70
Epson Research and Development
Vancouver Design Center
Memory
Clock
RAS#
CAS#
MA
WE#
MD(read)
MD(write)
t1
t3
t4 ^{t5 t6} t1
t8 ^{t9 t10 t11}
R
C1
C2
C3
C1
C2
t12
t21 t16
t14 t15
d1
d2
d3
t18 t19
d1
d2
Figure 7-19: FPM-DRAM Read-Write Timing
Table 7-18: FPM-DRAM Read/Write/Read-Write Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
Parameter
Internal memory clock period
Random read cycle REG[22h] bit 6-5 == 00
Random read cycle REG[22h] bit 6-5 == 01
Random read cycle REG[22h] bit 6-5 == 10
RAS# precharge time (REG[22h] bits 3-2 = 00)
RAS# precharge time (REG[22h] bits 3-2 = 01)
RAS# precharge time (REG[22h] bits 3-2 = 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 00 or 10)
RAS# to CAS# delay time (REG[22h] bit 4 = 1 and
bits 3-2 = 01)
RAS# to CAS# delay time (REG[22h] bit 4 = 0 and
bits 3-2 = 01)
CAS# precharge time
CAS# pulse width
RAS# hold time
Row address setup time (REG[22h] bits 3-2 = 00)
Row address setup time (REG[22h] bits 3-2 = 01)
Row address setup time (REG[22h] bits 3-2 = 10)
Min
40
5t1
4t1
3t1
2 t1 - 3
1.45 t1 - 3
1 t1 - 3
1.45 t1 - 3
2.45 t1 - 3
1t1 - 3
2t1 - 3
0.45 t1 - 3
0.45 t1 - 3
0.45 t1 - 3
2 t1 - 3
1.45 t1 - 3
1 t1 - 3
t7
C3
t17
t20
d3
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S1D13505
X23A-A-001-14
Hardware Functional Specification
Issue Date: 01/02/02