S1D13706 Datasheet, PDF (71/152 Pages) Epson Company – S1D13706 Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
Page 71
Sync Timing
FPFRAME
FPLINE
DRDY (MOD)
Data Timing
FPLINE
FPSHIFT
FPDAT[15:0]
t1
t2
t4
t3
t5
t6
t7
t8
t14
t9
t11 t10
t12 t13
1
2
Figure 6-26: Single Color 16-Bit Panel A.C. Timing
Table 6-22: Single Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[15:0] setup to FPSHIFT rising edge
FPDAT[15:0] hold to FPSHIFT rising edge
FPLINE falling edge to FPSHIFT rising edge
Min
Typ
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 3
5
2
2
2
2
note 8
1. Ts = pixel clock period
2. t1_min = HPS + t4_min
3. t2_min = t3_min - (HPS + t4_min)
4. t3_min = HT
5. t4_min = HPW
6. t5_min = HPS - 1
7. t6_min = HPS - (HDP + HDPS) + 2, if negative add t3_min
8. t14_min = HDPS - (HPS + t4_min), if negative add t3_min
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09