S1D13706 Datasheet, PDF (149/152 Pages) Epson Company – S1D13706 Embedded Memory LCD Controller

Epson Research and Development
Vancouver Design Center
Page 149
15 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13706 to accommodate
the need for power reduction in the hand-held devices market. This mode is enabled via the
Power Save Mode Enable bit (REG[A0h] bit 0).
Software Power Save Mode saves power by powering down the panel and stopping display
refresh accesses to the display buffer.
Table 15-1: Power Save Mode Function Summary
IO Access Possible?
Memory Writes Possible?
Memory Reads Possible?
Look-Up Table Registers Access Possible?
Sequence Controller Running?
Display Active?
LCD I/F Outputs
PWMCLK
GPIO Pins configured for HR-TFT/D-TFD²
GPIO Pins configured as GPIOs Access Possible?²
Software
Power Save
Yes
Yes¹
No¹
Yes
No
No
Forced Low
Stopped
Forced Low
Yes³
Normal
Yes
Yes
Yes
Yes
Yes
Yes
Active
Active
Active
Yes
Note
1 _{When power save mode is enabled, the memory controller is powered down and the}
status of the memory controller is indicated by the Memory Controller Power Save Sta-
tus bit (REG[A0h] bit 3). However, memory writes are possible during power save
mode because the S1D13706 dynamically enables the memory controller for display
buffer writes.
2 _{GPIO Pins are configured using the configuration pin CNF3 which is latched on the}
rising edge of RESET#. For information on CNF3, see Table 4-7: “Summary of Power-
On/Reset Options,” on page 28.
3 _{GPIOs can be accessed and if configured as outputs can be changed.}
After reset, the S1D13706 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
Hardware Functional Specification
Issue Date: 2004/02/09
S1D13706
X31B-A-001-09