S1D13706 Datasheet, PDF (48/152 Pages) Epson Company – S1D13706 Embedded Memory LCD Controller

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Table 6-11: Motorola REDCAP2 Interface Timing
Symbol
Parameter
2.0V
Min
Max
f_CKO
T_CKO
t1
Bus Clock frequency
Bus Clock period
Bus Clock pulse width low
17
1/f_CKO
26
t2 _{Bus Clock pulse width high}
26
t3 _{A[16:1], M/R#, R/W, CSn setup to CKO rising edge}
1
t4 _{A[16:1], M/R#, R/W, CSn hold from CKO rising edge}
0
t5a _{CSn asserted for MCLK = BCLK}
8
t5b _{CSn asserted for MCLK = BCLK ÷ 2}
10
t5c _{CSn asserted for MCLK = BCLK ÷ 3}
13
t5d _{CSn asserted for MCLK = BCLK ÷ 4}
15
t6 _{EB0, EB1 asserted to CKO rising edge (write cycle)}
1
t7 _{EB0, EB1 de-asserted to CKO rising edge (write cycle)}
1
t8 ^{D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1}
1
asserted low (write cycle) (see note 1)
t9 ^{D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1}
23
asserted low (write cycle)
t10 OE, EB0, EB1 setup to CKO rising edge (read cycle)
1
t11 OE, EB0, EB1 hold to CKO rising edge (read cycle)
1
t12 ^{D[15:0] output delay from OE, EB0, EB1 falling edge}
(read cycle)
4
29
t13a ^{1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]}
valid for MCLK = BCLK (read cycle)
4.5CKO
+7
t13b ^{1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]}
valid for MCLK = BCLK ÷ 2 (read cycle)
7CKO +
10
t13c ^{1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]}
valid for MCLK = BCLK ÷ 3 (read cycle)
8.5CKO
+8
t13d
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 4 (read cycle)
9CKO +
11
t14 CKO rising edge to D[15:0] output in Hi-Z (read cycle)
4
31
3.3V
Min
Max
17
1/f_CKO
26
26
1
0
8
10
13
15
1
4
0
8
0
0
3
10
4.5CKO +
20
6.5CKO +
20
9.5CKO +
20
11.5CKO
+ 20
1
11
Units
MHz
ns
ns
ns
ns
ns
T_CKO
T_CKO
T_CKO
T_CKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09