S1D13706 Datasheet, PDF (68/152 Pages) Epson Company – S1D13706 Embedded Memory LCD Controller

Page 68
Epson Research and Development
Vancouver Design Center
6.4.6 Single Color 8-Bit Panel Timing (Format 2)
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP
VNDP
Invalid
LINE1 LINE2 LINE3 LINE4
LINE239 LINE240
Invalid
LINE1 LINE2
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
2Ts Ts
HDP
2Ts 2Ts Ts 2Ts
Ts Ts
1-R1 1-B3
Ts
1-G6
1-G1 1-R4 1-B6
1-B1 1-G4 1-R7
1-R2 1-B4 1-G7
1-G2 1-R5 1-B7
1-B2 1-G5 1-R8
1-R3 1-B5 1-G8
1-G3 1-R6 1-B8
Ts Ts
2Ts Ts 2Ts
Ts Ts
1-G318
1-B318
1-R319
1-G319
1-B319
1-R320
1-G320
1-B320
HNDP
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-23: Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09