S1L30000 Datasheet, PDF (66/131 Pages) Epson Company – GATE ARRAY

Chapter 5: RAM
ADDRESS
CS
t _AS
WR
Data in
t _WC
t _WCS
t _AH
t _DH
t _DS
valid
Figure 5.7 Write Cycle (CS Control)
5.8 RAM Test Method
When it comes to internal RAM, specialized tests are performed corresponding to the RAM,
separate from the ramdom logic. Please structure test circuits which facilitate direct access to
the internal RAM from external pins for this purpose. See Section 6.3 of Chapter 6 regarding
the method of structuring the RAM test circuits.
Also, although EPSON will generate an independent test pattern for the RAM, the customer
should provide test patterns for the remaining random logic, in addition to a RAM test pattern
template, as shown in Section 6.3.1.
5.9 Estimating RAM Current Consumption
The method for estimating the current consumption at V_DD (Typ.) = 5.0 V is given below.
Moreover, for V_DD (Typ.) = 3.0 V or 3.3 V, the value is approximately 0.6 (60%) of the value
which is calculated using the method shown below.
(1) 1-Port RAM
At standby (CS = 0):0[µA/Bit]
During operation (CS = 1):0.18 x f[µA/Bit]f: MHz (average access cycles)
(2) 2-Port RAM
At standby (CS = 0):0[µA/Bit]
During operation (CS = 1):0.18 x f[µA/Bit]f: MHz (average access cycles)
60
EPSON
GATE ARRAY S1L30000 SERIES
DESIGN GUIDE