S1L30000 Datasheet, PDF (32/131 Pages) Epson Company – GATE ARRAY

Chapter 3: Cautions and Notes Regarding Circuit Design
(9) ATPG check sheet
Never delay sending this sheet a week before sending the logic circuit data. Please mark
“Yes” or “No” at each item.
1. Which the netlist format (gate level) interfaced to EPSON?
Verilog or EDIF
2. Is the scanned FF used at the original circuit? (Note 1)
Yes or No
3. Do you use macro cells, MSI cells and interval oscillator cells?
Yes or No
4. If you answer “Yes” to the question above, write the cell name. :
5. Do you use the internal 3-state bus?
Yes or No
6. Does your logic circuit have RS latch,
differential circuit and asynchronous circuit?
Yes or No
7. Do you use latch cells?
Yes or No
8. Is there a bi-direction pin?
Yes or No
9. Are there clocks that can not be directly controlled externally? Yes or No
10. Are there FF, reset and set pins of latch cells
that can not be directly controlled externally?
Yes or No
11. If the answers are “Yes” to question Nos.3 to 10, does the
circuit design correspond to the DFT rule? (Note 2)
Yes or No
12. Are I/O cells arranged on the top of the hierarchy?
Yes or No
13. Do the clocknets cope with skew by CTS?
Yes or No
Note1: If you answered “Yes”, please design the logic circuit again, because the circuit can not scan.
Note2: If you answered “No”, please insert the DFT, because the circuit can not scan. Also, if you ask to insert the
DFT to EPSON, please contact EPSON sales division, because circuit information in addition to that on this
sheet is required.
External Terminals
Enter the terminal names corresponding to the pin layout Table.
The specific terminals required vary by circuit configuration. (Be sure to enter all the terminal
names you need.)
• Clock Input Terminal
Terminal name: _______________ Operation edge:rise • fall
Terminal name: _______________ Operation edge:rise • fall
Terminal name: _______________ Operation edge:rise • fall
Terminal name: _______________ Operation edge:rise • fall
Terminal name: _______________ Operation edge:rise • fall
• Scan Enable Input Terminal (Note 3) ................................................................. Yes • No
Terminal name: _______________ Active level: High • Low
• ATPG Test Input Terminal ................................................................................ Yes • No
Terminal name: _______________ Active level: High • Low
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EPSON
GATE ARRAY S1L30000 SERIES
DESIGN GUIDE