S1L30000 Datasheet, PDF (56/131 Pages) Epson Company – GATE ARRAY

Chapter 5: RAM
5.4 Investigating RAM Placement on Master Slice
When investigating RAM placement on a master slice, please insure that sufficient area is
available in both the X direction (column) and the Y direction (row). When loading RAM onto a
chip, it is necessary to insure that the capacity of the master exceeds the required RAM area
in both the X and Y directions.
When multiple RAMs are used, RAM blocks are placed adjacent to each other either
horizontally or vertically; the decision regarding master slice selection is based simply on RX
and RY. Please see Table 1.1 of Chapter 1 regarding the number of columns (X-direction) and
number of rows (Y-direction).
For example, if five 128 word x 4 bit 1-port RAMs are required.
As shown in Figure 5.1, the total RAM layout area would be:
X direction: 143 BCs
Y direction: 85 BCs
Because of this,
S1L30182 is (X, Y) = (244, 76) is impossible due to area constraints, however,
S1L30302 is (X, Y) = (318, 97) is possible.
See Section 2.5 pertaining to estimating the number of gates, BC_AWR, which can be used for
random logic.
17
128w x 4b RAM ^{x 5}
143
17
17
85 17
17
17
RAM(1)
RAM(2)
RAM(3)
RAM(4)
RAM(5)
143
Figure 5.1 Example of RAM Layout
50
EPSON
GATE ARRAY S1L30000 SERIES
DESIGN GUIDE