S1L30000 Datasheet, PDF (27/131 Pages) Epson Company – GATE ARRAY

(4) Design Flow (2/2)
Chapter 3: Cautions and Notes Regarding Circuit Design
Customer
Seiko Epson
ATPG Rule Check
ATPG
Application Note
Temporary
Netlist
Logical check
ATPG
Check Sheet
Temporary
Pin Assignment
Circuit Block
Diagrams
ATPG Rule Check
Verification
HDL Design
RTL Creation TP Creation
ATPG Rule Check
Logic Synthesis
Pre-Simulation
Expected Values
of Input Patters
Netlist Circuit Data Pin Assignment
ATPG
ATPG Rule Check
Scan Insersion
Verilog-XL
Verification after ATPG
Verification of
Fault Detection Rate
OK or NG
Fault Detection
Netlist Circuit Data
P&R
P&R
Clock Tree Synthesis
Post-Simulation
Post-Simulation
Verification
Post-Simulation
Result List
Sign off
Figure 3.8 ATPG flow when designing by logic synthesis
GATE ARRAY S1L30000 SERIES
EPSON
21
DESIGN GUIDE