SED1353 Datasheet, PDF (6/30 Pages) Epson Company – SED1353 GRAPHICS LCD CONTROLLER

GRAPHICS
SED1353
s FUNCTIONAL BLOCK DESCRIPTION
Bus Signal Translation
According to configuration setting VD2, Bus Sig-
nal Translation translates either MC68000 type
MPU signals or Ready type MPU signals to
internal bus interface signals.
Control Registers
The Control Register contains 16 internal control
and configuration registers. These registers can
be accessed by either direct-mapping or using
the built-in internal index register.
Sequence Controller
The Sequence Controller generates horizontal
and vertical display timings according to the
configuration registers settings.
LCD Panel Interface
The LCD Panel Interface performs frame rate
modulation and output data pattern formatting
for both passive monochrome and passive color
LCD panels.
Look-Up Table
The Look-Up Table contains three 16x4-bit wide
palettes. In gray shade modes, the “green” pal-
ette can be configured for the re-mapping of 16
possible shades of gray. In color modes, all
three palettes can be configured for the re-map-
ping of 4096 possible colors.
Port Decoder
According to configuration settings VD1, VD12 -
VD4, IOCS# and address lines AB9-1, the Port
Decoder validates a given I/O cycle.
Memory Decoder
According to configuration settings VD15 -
VD13, MEMCS# and address lines AB19-17,
the Memory Decoder validates a given memory
cycle.
Data Bus Conversion
According to configuration setting VD0, Data
Bus Conversion maps the external data bus,
either 8-bit or 16-bit, into the internal odd and
even data bus.
Address Generator
The Address Generator generates display
refresh addresses to be used to access display
memory.
MPU / CRT Selector
The MPU / CRT Selector grants access to the
display memory from either the MPU or the dis-
play refresh circuitry.
Display Data Formatter
The Display Data Formatter reads in the display
data from the display memory and outputs the
correct format for all supported gray shade and
color selections.
Clock Inputs / Timing
Clock Inputs / Timing generates the internal
master clock according to gray-level / color
selected and display memory interface.The
master clock (MCLK) can be:
- MCLK = input clock
- MCLK = 1/2 input clock
- MCLK = 1/4 input clock.
Pixel clock = input clock = f_OSC.
SRAM Interface
The SRAM Interface generates the necessary
signals to interface to the Display Memory
(SRAM).
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