SED1353 Datasheet, PDF (1/30 Pages) Epson Company – SED1353 GRAPHICS LCD CONTROLLER

GRAPHICS
SED1353
SED1353 GRAPHICS LCD CONTROLLER
October 1998
s DESCRIPTION
The SED1353 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is
capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades.
Design flexibility allows the SED1353 to interface to either an MC68000 family microprocessor or an
8/16-bit MPU/bus with minimum external logic. The Static RAM (SRAM) interface used for the display buffer
is optimized for speed and performance, supporting up to 128K bytes.
Two power save modes, combined with operating voltages of 2.7 volts through 5.5 volts, allow for a wide
range of applications while providing minimum power consumption.
s FEATURES
• pin compatible with the SED1352
• 16-bit 16 MHz MC68xxx MPU interface
• 8/16-bit MPU interface controlled by a READY
(or WAIT#) signal
• option to use built-in index register or direct-map-
ping to access one of sixteen internal registers
• 2-terminal crystal or external oscillator support
• 8/16-bit SRAM interface configurations
• split screen display support allowing two different
images to be simultaneously displayed
• virtual display support (displays images larger
than the panel size through the use of panning)
• display modes:
black-and-white display
2/4 bits per pixel, 4/16-level gray-scale display
2/4/8 bits per pixel, 4/16/256-level color display
• two software power-save modes
• low power consumption
• display memory interface:
128K bytes using one 64Kx16 SRAMs
128K bytes using two 64Kx8 SRAMs
64K bytes using two 32Kx8 SRAMs
40K bytes using one 8Kx8 and one 32Kx8
SRAM
32K bytes using one 32Kx8 SRAM
16K bytes using two 8Kx8 SRAMs
8K bytes using one 8Kx8 SRAM
• LCD panel configurations:
single-panel, single-drive passive display
dual-panel, dual-drive passive display
• maximum number of vertical lines:
1,024 lines (single-panel, single-drive display)
2,048 lines (dual-panel, dual-drive display)
• QFP5-100-S2 package (F0A)
• QFP15-100-STD package (F1A)
s SYSTEM BLOCK DIAGRAM
CLOCK
MPU
80xx
Z80
68xxx
DATA
CONTROL
ADDRESS
SED1353
LCD PANEL
SRAM
X18A-C-001-08
1