SED1353 Datasheet, PDF (17/30 Pages) Epson Company – SED1353 GRAPHICS LCD CONTROLLER

GRAPHICS
SED1353
Clock Inputs
Pin Name Type
F0A
Pin #
OSC1
I
92
OSC2
O
93
Power Supply
Pin Name Type
V_DD
P
V_SS
P
F0A
Pin #
3, 53
2, 52
F1A
Pin #
89
90
D0A
Pad #
115
116
Description
This pin, along with OSC2 is the 2-terminal crystal interface when using a
2-terminal crystal as the clock input. If an external oscillator is used as a
clock source, then this pin is the clock input.
This pin, along with OSC1 is the 2-terminal crystal interface when using a
2-terminal crystal as the clock input. If an external oscillator is used as a
clock source, then this pin should be left unconnected.
F1A
Pin #
50, 100
49, 99
D0A
Pad #
3, 67
1, 65
Description
Voltage supply.
Voltage Ground.
s SUMMARY OF CONFIGURATION OPTIONS
Pin Name value on this pin at falling edge of RESET is used to configure:
(1/0)
1
0
VD0
16-bit host bus interface
8-bit host bus interface
VD1
Use direct-mapping for I/O accesses
Use indexed mapping for I/O accesses
VD2
MC68000 MPU interface
MPU / Bus interface with memory accesses controlled
by a READY (WAIT#) signal
VD3
Swap of high and low data bytes in 16-bit bus interface
No byte swap of high and low data bytes in 16-bit bus
interface
Select I/O mapping address bits [9:1].
VD12-VD4
These nine bits are latched on power-up and are compared to the MPU address bits [9-1]. A valid I/O cycle
combined with a valid address will enable the internal I/O decoder. Therefore, both types of I/O mapping are
limited to even address boundaries to determine either the absolute or indexed I/O address of the first register.
Note that a “valid I/O cycle” includes IOCS# being toggled low.
Select memory mapping address bits [3:1]
These three bits are latched on power-up and are compared to the MPU address bits [19-17]. A valid memory
cycle combined with a valid address will enable the internal memory decoder. As only the three most significant
VD15-VD13 bits of the address are compared, the maximum amount of memory supported is 128K bytes. Note that a “valid
memory cycle” includes MEMCS# being toggled low.
When using 128K byte memory it must be mapped at an even address such that all 128K bytes is available without
a change in state on A17, as this would invalidate the internal compare logic.
X18A-C-001-08
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