SED1353 Datasheet, PDF (16/30 Pages) Epson Company – SED1353 GRAPHICS LCD CONTROLLER

GRAPHICS
SED1353
Display Memory Interface
F0A
Pin Name Type
Pin #
F1A
Pin #
D0A
Pad #
VD0-VD15 I/O
44 - 51,
54 - 61
41 - 48,
51 - 58
54-55,
57-61,
64,
68-75
VA0-VA15 O
VCS1# O
VCS0# O
VWE#
O
VOE#
O
33 - 43, 30 - 40
62 - 66 59 - 63
69
66
68
65
38-40,
42-43,
45-46,
48-49,
51-52,
77-81
84
83
67
64
82
83
80
102
Description
These pins are connected to the display memory data bus. For 16-bit interface,
VD0-VD7 are connected to the display memory data bus of even byte addresses
and VD8-VD15 are connected to the display memory data bus of odd byte
addresses. The output drivers of these pins are tri-stated when RESET is high.
On the falling edge of RESET the values of VD0-VD15 are latched into the chip
to configure various hardware options.
These pins are connected to the display memory address bus.
Active low chip-select output to the second or odd byte address SRAM.
Active low chip-select output to the first or even byte address SRAM.
Active low output used for writing data to the display memory. This pin is
connected to the WE# input of the SRAMs.
Active low output to enable reading of data from the display memory. This pin is
connected to the OE# input of the SRAMs.
LCD Interface
FPDI-1^TM
F0A
Pin Name
Pin Name^a
Type
Pin #
F1A
Pin #
D0A
Pad #
UD3-UD0 UD3-UD0
LD3-LD0 LD3-LD0
O
70 - 73 67 - 70 86 - 89
74 - 77 71 - 74 90 - 93
XSCL
FPSHIFT O 81
78
100
LP
FPLINE O 79
76
96
MOD
WF/XSCL2
O 80
77
97
FPSHIFT2
YD
FPFRAME O 78
75
94
LCDENB ---
O 82
79
101
a. VESA Flat Panel Display Interface Standard (FPDI-1^TM)
Description
Panel display data bus. The data format depends on the specific
panel connected. For 4-bit single panels, these bits are driven 0
(low state).
Display data shift clock. Data is shifted into the LCD X-drivers on
the falling edge of this signal.
Display data latch clock. The falling edge of this signal is used to
latch a row of display data in the LCD X-drivers and to turn on the
row driver (Y driver).
For format 1 of 8-bit single color panels this is the second shift
clock. For all other modes,this is the LCD backplane BIAS signal.
This output toggles once every n LP periods, as programmed in
AUX[05]
Vertical scanning start pulse. A logic ‘1’ on this signal, sampled
by the LCD module on the falling edge of LP, is used by the panel
row driver (Y driver) to indicate the start of the vertical frame.
LCD enable signal output. It can be used externally to turn off the
panel supply voltage and backlight.
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X18A-C-001-08