SED1353 Datasheet, PDF (15/30 Pages) Epson Company – SED1353 GRAPHICS LCD CONTROLLER

GRAPHICS
SED1353
s PIN DESCRIPTION
Key
I = Input
O = Output
I/O = Bidirectional
P = Power
Bus Interface
Pin Name
Type
F0A
Pin #
F1A
Pin #
D0A
Pad #
Description
DB0-DB15 I/O
94 - 100, 91 - 98,
1, 4 -11 1 - 8
118-119,
121-125, These pins are connected to the system data bus. In 8-bit bus mode, DB8-
128,
DB15 must be tied to V_DD.
4-11
In MC68000 MPU interface, this pin is connected to the Upper Data Strobe
AB0
I 12
9
13
(UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the
system address bus.
AB1-AB19 I
BHE#
I
IOCS#
I
13 - 31
10 - 28
14-20,
22-30,
32-33,
36
91
88
113
84
81
103
These pins are connected to the system address bus.
In MC68000 MPU interface, this pin is connected to the Lower Data Strobe
(LDS#) pin of MC68000. In other bus interfaces, this pin is the Byte High
Enable input for use with 16-bit system. In 8-bit bus mode, tie BHE# input to
V_DD.
Active low input to select one of fifteen internal registers.
In MC68000 MPU interface, this pin is connected to the R/W# pin of
IOW#
I 85
82
104
MC68000. This input pin will define whether the data transfer is a read
(active high) or write (active low) cycle. In other bus interfaces, this is the
active low input to write data into an internal register.
In MC68000 MPU interface, this pin is connected to the AS# pin of
IOR#
I 86
83
106
MC68000. This input pin will indicate a valid address is available on the
address bus. In other bus interfaces, this is the active low input to read data
from an internal register.
MEMCS# I 87
84
107
Active low input to indicate the attempt to access the display memory.
MEMW# I 88
85
109
Active low input to write data to the display memory. This pin should be tied
to V_DD in an MC68000 MPU interface.
MEMR# I 89
86
110
Active low input to read data from the display memory. This pin should be
tied to V_DD in an MC68000 MPU interface.
For MC68000 MPU interface, this pin is connected to the DTACK# pin of
MC68000 and will be driven low when ever a data transfer is complete. In
other bus interfaces, this output is driven low to force the system to insert
READY O 90
87
112
wait states when needed.
READY is placed in a high-impedance (Hi-Z) state after the transfer is
completed.
RESET I 32
29
37
Active high input to force all signals to their inactive states.
X18A-C-001-08
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