S1D13A05B00B200 Datasheet, PDF (43/184 Pages) EPCOS – LCD/USB Companion Chip

Epson Research and Development
Vancouver Design Center
Page 43
Table 6-14: Motorola MC68K#2 Interface Timing
Symbol
f_CLK
T_CLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Parameter
Bus clock frequency
Bus clock period
A[16:0], M/R#, R/W#, SIZ[1:0] and CS# and AS# and DS# setup to
first CLK rising edge
CS# and AS# asserted low to DSACK1# driven
A[16:1], M/R#, R/W#, SIZ[1:0] hold from AS# rising edge
CS# hold from AS# rising edge
DS# rising edge to AS# rising edge
AS# setup to CLK falling edge
DSACK1# falling edge to DS# rising edge
CLK rising edge to DSACK1# falling edge
AS# rising edge to DSACK1# rising edge
1st CLK falling edge after AS# deasserted to DSACK1# high
impedance
D[15:0] setup to 4th CLK rising edge after CS#=0, AS#=0, DS#=0,
and DSACK1#=0
D[15:0] hold from DSACK1# falling edge
D[15:0] valid setup to DSACK1# falling edge (read cycle)
DS# rising edge to D[15:0] high impedance (read cycle)
Cycle Length
Min
1/f_CLK
0
2
0
0
0
1
0
5
3
1
0
0.5
2
7
Max
50
7
14
9
T_CLK + 3
9
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T_CLK
ns
T_CLK
ns
T_CLK
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
S1D13A05
X40A-A-001-07