S1D13A05B00B200 Datasheet, PDF (149/184 Pages) EPCOS – LCD/USB Companion Chip

Epson Research and Development
Vancouver Design Center
Page 149
bit 1
Reserved.
This bit must be set to 0.
bit 0
Reserved.
This bit must be set to 0.
Reserved
REG[4042h]
n/a
15
14
13
12
11
10
9
8
n/a
7
6
5
4
3
2
1
0
Pin Input Status / Pin Output Data Register
REG[4044h]
Default = depends on USB input pin state
n/a
15
14
13
12
11
n/a
7
6
5
4
3
Read/Write
10
9
8
USBDETECT
Input Pin Status
(read only)
USBPUP Output
Pin Status
2
1
0
These bits can generate interrupts.
bit 1
USBDETECT Input Pin Status
This read-only bit indicates the status of the USBDETECT input pin after a steady-state
period of 0.5 seconds.
bit 0
USBPUP Output Pin Status
This bit controls the state of the USBPUP output pin.
This bit must be set to 1 to enable the USB interface and USB registers. See the S1D13A05
Programming Notes and Examples, document number X40-A-G-003-xx for further infor-
mation on this bit.
Interrupt Control Enable Register 0
REG[4046h]
Default = 00h
15
14
13
n/a
USB Host
Connected
Reserved
7
6
5
n/a
12
11
Reserved
Reserved
4
3
10
Reserved
2
Read/Write
9
USBRESET
1
8
Reserved
0
These bits enable interrupts from the corresponding bit of the Interrupt Control Status/Clear
Register 0.
0 = corresponding interrupt bit disabled (masked).
1 = corresponding interrupt bit enabled.
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
S1D13A05
X40A-A-001-07