S1D13A05B00B200 Datasheet, PDF (133/184 Pages) EPCOS – LCD/USB Companion Chip

Epson Research and Development
Vancouver Design Center
Page 133
Type 3 TFT Partial Area 2 Positions Register
REG[F0h]
Default = 00000000h
n/a
Partial Area 2 Y End Position bits 5-0
31
30
n/a
15
14
29
28
27
26
25
24
Partial Area 2 Y Start Position bits 5-0
13
12
11
10
9
8
n/a
23
22
n/a
7
6
Read/Write
Partial Area 2 X End Position bits 5-0
21
20
19
18
17
16
Partial Area 2 X Start Position bits 5-0
5
4
3
2
1
0
bits 29-24
Partial Area 2 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 21-16
Partial Area 2 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 13-8
Partial Area 2 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0
Partial Area 2 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Type 3 TFT Command Store Register
REG[F4h]
Default = 00000000h
Read/Write
n/a
Command 1 Store bits 11-0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
n/a
Command 0 Store bits 11-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
bits 27-16
Command 1 Store Bits [11:0]
These bits store command 1 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
bits 11-0
Command 0 Store Bits [11:0]
These bits store command 0 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
S1D13A05
X40A-A-001-07